The present invention relates generally to the operation of integrated circuits (ICs) at power-up, and more particularly to methods of pre-configuring initial operational modes of an integrated circuit to be entered upon power up.
Various integrated circuits, e.g., microcontrollers and systems-on-a-chip (SoCs), are used in portable, battery-powered devices, such as laptop computers and cellular phones. An important concern in any battery-powered device is extending the amount of time the device can be used before the battery requires recharging.
There are a number of techniques used to provide power management to the various subsystems within such devices in order to conserve battery power and to meet energy-star requirements. Most of these techniques depend upon some monitoring of the various subsystems by code executing on the processing subsystems of the hardware. For example, some computer systems, such as those disclosed in U.S. Pat. No. 4,980,836 (“the '836 patent”), utilize centralized, power management control of various peripheral devices, such as floppy-disk drives and hard-disk drives, in order to conserve battery power.
More particularly, in the system disclosed in the '836 patent, access to the various peripheral devices, such as the floppy-disk drive and the hard-disk drive, is monitored. If the peripheral devices have not been accessed for a predetermined amount of time, the peripherals and/or the computer system may be placed in a low-power state by a centralized, power management control logic circuit.
To achieve the low-power state, the system clock frequency may be reduced in order to reduce the power consumption of the device. By stopping the system clock, the power consumption is significantly reduced, particularly since CMOS devices typically used in such SoCs use extremely low power at zero frequency. Other power management schemes may use a reduction in voltage or a combination of frequency and voltage management schemes to conserve power in low-power modes.
However, in the above scenarios, a significant amount of time may pass between when the system powers up and when the peripherals are placed into the low-power state. During this time, a good deal of energy may be lost unnecessarily.
In other IC power management schemes, power is managed at a system-on-a-chip (SoC) or multi-chip module (MCM) level rather than on a system level. For example, U.S. Pat. No. 6,665,802 discloses a decentralized power management scheme where the peripherals themselves are in control of their own power usage state (e.g., high or low).
In U.S. Pat. No. 7,181,188, a method and apparatus are disclosed for an SoC to enter a low-power mode following a trigger from a power master.
Some exemplary ICs featuring advanced clock and power management techniques are included in the i.MX280 Multimedia Applications Processor family manufactured by Freescale Semiconductor, Inc. of Austin, Tex. A datasheet for this family of SoCs may be downloaded from http://cache.freescale.com/files/32 bit/doc/data_sheet/IMX28CEC.pdf?pspll=1. The datasheet is incorporated herein by reference in its entirety.
ICs are developed in a series of steps. At a top level, ICs are typically designed using a hardware description language such as Verilog or VHDL. The language is run through a hardware compiler and simulator, and then eventually the design phase culminates with “tape-out,” the point at which artwork for an IC photomask is sent to a wafer fabrication facility. Following tape-out, a wafer is manufactured that includes one or more copies of the IC, the copies being known as semiconductor dies. Following wafer fabrication, wafer testing is performed, then the IC dies are cut from the wafer and further testing, configuration, and packaging of the dies is done.
For some ICs, during the design phase, the ICs are targeted for a specific application, such as remote sensing, where power is at a premium. Such ICs may be designed to power up directly into a low-power mode following application of power. These ICs might not have the flexibility to run code after they boot to change their operational mode. However, even if they can change their operational mode after booting up, these ICs will waste time (and power) changing from a low-power and typically lower performance operational mode to the potentially desired higher performance operational mode.
Some ICs/SoCs may support a wide variety of run-time applications requiring different power profiles, but they must always reach these different power profiles after executing code in their default power-up profile. For example, a SoC used in a cell phone may power up in a default operational mode, check the battery status, and adjust its operating mode to a lower-power mode, where, for example, the primary graphics display driver is powered down.
Disadvantageously, such an SoC always first passes through its default operational mode before being programmed into a lower-power, high performance, or otherwise preferred state, thereby wasting energy in the time spent in the normal operational mode as well as in the power-mode transition itself. Further, when the preferred mode is a high-performance mode, a SoC that boots to a default mode before it can change to the high performance mode will appear less responsive than one that is designed to boot directly to a high performance mode. A SoC may be designed to run in a low-power state, for example, for application in a satellite telemetry system, but this same SoC may never be used in a high power application.
Thus, additional flexibility in the utilization of the same IC design for various power/performance profiles is desired so that one IC design may be used in a variety of applications.